IC Packages

Note: Each family has many variants (body sizes, lead‑pitches, thermal options, ceramic vs. plastic). Always consult the specific device’s datasheet for exact package dimensions, pin‑outs and thermal/PCB‑layout recommendations.

Image	Package	Full Name & Style	Mounting	Typical Pin‑Count Range	Notes
	DIP	Dual Inline Package	Through‑hole	4 – 64	Legacy logic, microcontrollers, prototyping
	SIP	Single Inline Package	Through‑hole	4 – 16	Resistor/diode networks, simple modules
	PGA	Pin Grid Array	Through‑hole	64 – 500	CPUs, high‑end DSPs, socketed devices
	ZIP	Zig‑Zag Inline Package	Through‑hole	8 – 20	Older memory and logic modules (now rare)
	PLCC	Plastic Leaded Chip Carrier	SMT	20 – 84	PLDs, FPGAs, EEPROMs
	SOJ	Small Outline J‑lead	SMT	24 – 52	DRAM chips, some logic ICs
	TSOP	Thin Small Outline Package	SMT	8 – 60	Flash memory (NAND/NOR), slim modules
	TSSOP	Thin Shrink Small Outline Package	SMT	8 – 80	ADCs, interface ICs, where board space is tight
	QFP	Quad Flat Package	SMT	32 – 304	Microcontrollers, DSPs; variants include LQFP, HTQFP…
	TQFP	Thin Quad Flat Pack (gull‑wing leads on four sides)	SMT	32 – 176 (up to ≈208)	Low‑profile QFP; lead pitches usually 0.5 mm or 0.8 mm.
	VQFN	Very thin Quad Flat No‑leads (exposed pad underside)	SMT	8 - 100	No gull‑wing leads—contacts are pads on package edges; Power ICs, sensors; exposed thermal pad underside
	QFN / DFN	Quad/Dual Flat No‑lead	SMT	8 – 100	Same as VQFN; some call smaller DFN
	MLF / LFCSP	MicroLeadFrame / LeadFrame CSP	SMT	8 – 128	Power management, interface ICs; exposed pad
	CSP / WLCSP	Chip‑Scale Package / Wafer‑Level CSP	SMT	4 – 256	Mobile SoCs, RF chips; minimal package size
	BGA	Ball Grid Array	SMT	36 – 2600+	High‑pin CPUs, FPGAs, GPUs—excellent thermal & signal
	LGA	Land Grid Array	SMT	60 – 1700	Some server CPUs; flat lands instead of balls
	SOIC	Small Outline IC (gull‑wing dual‑in‑line)	SMT	8 - 28	Medium‑density logic; Standard lead pitch 1.27 mm; “wide” SOIC bodies support up to 28 pins.
	SSOP	Shrink Small Outline Package (narrow SOIC)	SMT	8 – 56	ASICs, memories; Lead pitch typically 0.5 mm or 0.635 mm; body narrower than SOIC.
	SOT‑23	Small Outline Transistor	SMT	3 – 6	Discrete transistors, small regulators
	SOT‑223	Small Outline Transistor (power variant)	SMT	4	Low‑power regulators, amplifiers

Brief Descriptions

DIP

Dual Inline Package: Two parallel rows of straight leads. Common on microcontrollers, legacy logic, prototyping.

SIP

Single Inline Package: One row of pins. Used for resistor/diode networks, modules.

PGA

Pin Grid Array: Grid of pins on bottom. Often CPUs (Socket‑type) and high‑end DSPs.

ZIP

Zig‑Zag Inline Package: Pins staggered in a zig‑zag down one side. Less common today.

PLCC

Plastic Leaded Chip Carrier: Square body with J‑leads. Was popular for PLDs, FPGAs, EEPROMs.

SOJ

Small Outline J‑lead: Like SOIC but with J‑shaped leads. Used on DRAM and some logic.

TSOP

Thin Small Outline Package: Very low‑profile SOP (pitch ≈ 1.0 mm). Widely used for flash memory.

TSSOP

Thin Shrink Small Outline Package: Narrower, finer‑pitch SOP (pitch 0.5–0.65 mm). Common for ADCs, interfaces.

QFP

Quad Flat Package: Gull‑wing leads on four sides. Variants: LQFP, HTQFP, etc.

TQFP

Thin Quad Flat Pack: A thinner variant of the classic QFP. Leads extend from all four sides in a gull‑wing style. Widely used for microcontrollers and DSPs where moderate to high pin counts (32–176) are needed in a slim form.

VQFN

Very thin Quad Flat No‑leads: A low‑profile “no‑leads” package: metal pads sit flush on the PCB; an exposed pad under the package provides heat‑dissipation. Common for RF, power, and high‑density logic ICs. Starts as low as 8 pins and goes up to around 100 pins.

QFN / DFN

Quad/Dual Flat No‑lead: No gull‑wings—contacts are pads. Includes DFN, SON. Used for power‑ICs, sensors.

MLF / LFCSP

MicroLeadFrame / LeadFrame CSP: A QFN‑style leadframe with exposed pad. Power management, interface ICs.

CSP / WLCSP

Chip‑Scale Package / Wafer‑Level CSP: Bare‑die sized package with solder bumps. Mobile SoCs, RF chips.

BGA

Ball Grid Array: Array of solder balls underneath. High‑pin CPUs, FPGAs, GPUs.

LGA

Land Grid Array: Array of flat lands (no balls). Seen on some server CPUs.

SOIC

Small Outline IC: A very common DIP‑replacement: gull‑wing leads on two sides. Pin counts start at 8 and usually top out at 28 for the “wide” body; it’s a go‑to for medium‑density logic.

SSOP

Shrink Small Outline Package: Essentially a “shrink” SOIC with finer pitch leads (0.5 – 0.635 mm), allowing more pins (up to 56 in some families) in a narrower footprint. Popular for ASICs and memory devices where board‑space is at a premium.

SOT‑23

Small Outline Transistor: Tiny 3‑pin (or 5‑pin) package. Common discrete transistors/regulators.

SOT‑223

Small Outline Transistor (power variant): 4‑lead power package. Low‑power regulators, small amplifiers.